Non-volatile memory systems, such as solid state drives (SSDs) including NAND flash memory, are commonly used in electronic systems ranging from consumer products to enterprise-level computer systems. Controllers in some SSDs often manage high throughput data traffic between one or more hosts and the multiple non-volatile memory die in the SSD. The high throughput combined with larger numbers of non-volatile memory die can result in processing demands in the SSD that lead to the need for a multi-processor controller. However, some host controller interface standards, such as non-volatile memory express (NVMe), allow a large number of tasks to be performed out of order by a multi-processor controller and may present a challenging problem of managing multiple processors in a SSD concurrently. Another challenge that may arise in a multi-controller SSD is the need to prevent data conflicts, such as one processor reading invalid data before a request was completed by another processor in the SSD.
Some prior multi-processor SSD architectures utilized two data path processors, each with a respective command queue, where commands were copied between the two different command queues. In order to copy commands between queues, a shared memory buffer was used. To protect a shared data resource, a software tool called mutual exclusion (mutex) is often used. A mutex is meant to be taken and released, always in that order, by each task that uses the shared resource it protects. However, locking of a processor in a multi-processor SSD by a mutex may occur in a multi-processor architecture. This is because the mutex operates such that only one processor can access the shared resource at a time and other processors are forced to wait until the resource is released by the first processor.